Semiconductor devices are continuously improved to enhance device performance. For example, both smaller device size and higher speed of operation are highly desirable performance targets. Transistors have also been continuously reduced in size to lower the power consumption and to increase the clocking frequency. By constructing smaller gate structures for complementary metal oxide silicon (CMOS) transistors, it becomes possible to pack more transistors on the same surface area. The reduction in the size of the gate structures has led to a substantial decrease of the electrical thickness of the gate dielectric to 3 nm and less in today's technologies.
The main elements of a typical MOS semiconductor device are shown in FIG. 1. The device generally includes a semiconductor substrate 101, on which a gate stack is disposed. The gate stack comprises a gate dielectric layer 110 and a gate electrode 114 disposed on the gate dielectric layer 110. The gate electrode 114 acts as a conductor. An input signal is typically applied to the gate electrode 114 via a gate terminal (not shown). Lightly doped drain (LDD) regions 103 reduce the electric field near the drain edge and thus reduce the incident of hot carrier generation. Spacers 111, usually consisting of an insulating oxide, are formed in the sidewalls. Then, heavily doped source/drain regions 102 are formed in the semiconductor substrate 101 and are later connected to source/drain terminals (not shown).
A channel region 116 is formed in the semiconductor substrate beneath the gate dielectric 110 and it separates source/drain regions 102. The channel region is typically lightly doped with a dopant of a type opposite to that of the source/drain regions 102. The gate electrode 114 is separated from the semiconductor substrate 101 by the gate dielectric layer 110. The insulating gate dielectric layer 110 is provided to prevent current from flowing between the gate electrode 114 and the source/drain regions 102 or the channel region 116. The properties of the transistor critically depend on the thickness and quality of the gate dielectric layer 110.
In a CMOS device, opposite type NMOS 300 and PMOS 350 transistors are present as shown in FIG. 3. By applying a voltage to the gate electrodes 314, 364 of the transistors, channel regions 316, 366 become electrically conductive in the lightly doped substrate regions beneath the gate dielectrics 310, 360. The transistor switches from a non-conductive state into a conductive state at the threshold voltage that is applied to the gate electrode. In order to keep the threshold voltages of the transistors small and, hence, to keep the power consumption of the transistors low, the work function of the gate electrode material should be approximately equal to the work function of the substrate material underneath the gate electrode.
P-type and N-type substrate materials have significantly different work functions. Traditionally, the work function matching was achieved by using polysilicon as gate electrode material and by doping the polysilicon with a dopant of the same type as the substrate material directly underneath the gate electrode. However, in current technology, polysilicon is not adequate anymore because of its too low conductivity and because of depletion effects. The depletion takes place in the semiconducting polysilicon at the gate electrode/gate dielectric interface, increasing the equivalent oxide thickness (EOT) of the gate dielectric. On the other hand, the solubility of the dopants of the polysilicon is limited to about 5×1020 atoms/cm3. The solubility restricts the amount of charge carriers formed in polysilicon. Therefore, nowadays more conductive materials, such as refractory metals, e.g. tungsten, are used. In practice, metallic materials have infinite amount of carriers (5×1022 atoms/cm3) and therefore the thickness of depletion region is virtually zero. This leads to a decrease of 4–5 Å of the EOT of the gate dielectric.
The most important property of the metal gate is its work function, which together with the doping level of the substrate determines the threshold voltage of the metal oxide semiconductor device. The work function of the metal electrode material should be about 4.0 to 4.2 eV in NMOS field effect transistors and about 5.0 to 5.2 eV in PMOS field effect transistors.
Thus, a need exists for adjusting the work function of the conductor. Features known to influence the work function of the metal electrode material are: the deposition method of the metal electrode, the heat treatments carried out after the deposition (i.e. RTA, Rapid Thermal Annealing), the thickness of the metal electrode layer, the gate oxide material used and the crystal orientations of the electrode material. The influence of the heat treatments on the work function of the electrode material is possibly due to crystallization of the materials or, for example, to emission of stoichiometrically superfluous nitrogen or some other element from the material during heat treatment. It is known that when a metal is oxidized or nitridized its average electronegativity is increased. Since work functions scale with electronegativity, the increase of electronegativity also increases the work function.
Attempts have been made to modify the work functions of metal gate materials by doping after the metal gate film deposition. However, work functions of metal gate materials after doping are not easily predictable and controllable. Doping of the gate material after the deposition can change not only the stoichiometry of the film but also the crystal orientation of the films (Q. Lu et al., Symp. VLSI Tech. (2001) 45–46 and U.S. Patent Application Ser. No. 2002/0008257 A1).
U.S. Pat. No. 6,458,695 B1 discloses a method of adjusting the work function of an electrode by controlling the composition of the material. The publication describes the deposition of metal gates followed by oxidizing or oxygen implanting the metal gate electrode for one or both types of transistors so that an alloy is formed of the metal and its conductive oxide, the alloy having a desired work function.
U.S. Pat. No. 6,506,676 discloses a method of changing the work function of an electrode comprising titanium, aluminum and nitrogen by changing the composition of (TixAly)1-zNz. According to the method, atomic layer deposition can be applied to change the composition of the film. During the time between cycles when the (TixAly)1-zNz film is deposited using the precursors, one of NH3, N2 and ND3 may be used for purging materials in order to adjust the nitrogen (N) content. At this time, the composition of nitrogen (N) is controlled by the number of each of the cycles.
In a U.S. Pat. No. 6,518,106 Ngai et al. disclose a method of changing the composition and thus the work function of a gate electrode in a transistor with ALD by changing the concentration of one element in the gate electrode material. According to the method of U.S. Pat. No. 6,518,106 B2 the work function of a metal gate layer is changed when the concentration of silicon or nitrogen is changed in layers that contain metal, silicon and nitrogen (e.g. TaSiN). Atomic layer deposition (ALD), chemical vapor deposition (CVD) and physical vapor deposition (PVD) have been disclosed as examples of methods for depositing the metal gate layer. However, a method avoiding local concentration variations over the substrate is not disclosed.
Ru—Ta-alloys have also been studied for use as gate electrodes. The work function of the ruthenium-tantalum metal electrodes could be adjusted to a value between 4.2 and 5.1 eV by using different Ru—Ta compositions. The work function of metal electrodes containing more ruthenium was close to 5 eV and an electrode with the composition Ru0.60Ta0.40 had a work function of about 4.3 eV (H. Zhong et al. Appl. Phys. Lett. 78 (2001) 1134–1136). However, the electrodes were formed by PVD method, resulting in sputtering damage on the gate stack dielectric layer and furthermore, causing non-uniformities in electrical and physical properties of ultra-thin films over the substrate.
Tuning of the work function of an electrode can also be achieved by a two-layer electrode structure, each layer having a different work function as described in a U.S. Pat. No. 6,373,111. When the bottom electrode layer is thin, preferably below 3 nm, the work function of the electrode structure will primarily be determined by, and be equal to, the work function of the top layer. When the bottom layer is thick, preferably above 10 nm, the work function of the electrode structure will primarily be determined by, and equal to, the work function of the bottom layer. In a transition region, between 3 and 10 nm, the work function of the electrode structure can be adjusted between the work function of the top layer and the work function of the bottom layer by adjusting the thickness of the bottom film.
Crystal orientation has a significant effect on the work function of the gate electrode. For example, tungsten with a crystallite orientation of 110 (W<110>) has a maximum work function value of 5.25 eV and W<113> a minimum work function value of 4.18 eV (H. B. Michaelson, J. Appl. Phys. 48 (1977) pp. 4729–4733). This indicates that it is theoretically possible to make both gate electrodes of CMOS devices from the same material, because the acceptable limit is 4.0–4.2 eV for NMOS and 5.0–5.2 eV for PMOS. It has been observed that by implanting the gate electrode material with 1–2 at.-% of nitrogen and after some annealing the work function value of the gate electrode changed so much that the change could not be explained by only the increased nitrogen concentration (R. Lin et al., IEEE Electron Dev. Lett. 23 (2002) pp. 49–51).
A problem associated with the known methods of tuning the work function of a gate stack is that several variables are involved simultaneously, which makes it very difficult to control the tuning. The composition of the gate electrode is one of the major factors affecting the work function. However, gate electrode layers having the same thickness and same chemical compositions, but deposited by different depositing techniques, such as PVD and ALD, have different work functions. Another problem of the above-described methods is that adequate control of film composition, uniformities and profiles, or thickness cannot be achieved. Further, subjecting the gate electrode material to an oxidizing ambient subjects the gate dielectric material also to the oxidizing ambient, which might detrimentally affect the dielectric material and oxidize the underlying substrate material.
Therefore, there is a need for a method of adjusting the work function of a gate electrode material in a gate stack and a method that avoids the above-described disadvantages.